The basis of the microcontroller (see Fig. 1) is an 8-bit Arithmetic Logic Unit (ALU). The memory of the MK has a Harvard architecture, i.e. logically divided: into program memory - PP (internal or external), addressed by a 16-bit command counter (SC) and data memory - internal (Resident data memory - RPD) 128 (or 256) bytes, as well as external (External data memory – VPD) up to 64 KB. Physically, program memory is implemented on ROM (read only), and data memory is implemented on RAM (data can be written and read).

Reception and delivery of external signals is carried out through 4 eight-bit ports Р0..Р3. When referring to external memory programs (VPP) or data memory (VPD) ports P0 and P2 are used as a multiplexed external bus Address / Data. P3 port lines can also perform alternative functions (see Table 1).

The 16-bit DPTR register forms the VPD address or Program Memory base address in the Accumulator conversion instruction. The DPTR register can also be used as two independent 8-bit registers (DPL and DPH) to store operands.

8-bit internal command register (RK) receives the code of the command being executed; this code is decoded by the control circuit, which generates control signals (see Fig. 1).

Access to special function registers - RSF (SFR - in Fig. 1 they are circled with a dotted line) is possible only using direct byte addressing in the address range from 128 (80h) and more.

Resident data memory (RDD) in the first models of microcontrollers of the MCS-51 family had a capacity of 128 bytes. The lower 32 bytes of the RPD are also general-purpose registers - RON (4 banks of 8 RONs each). The program can apply to one of the 8 RONs of the active bank. The selection of the active bank of RONs is carried out by programming two bits in the processor status register - PSW.

Table 1 - MCS-51 pin assignment

Switching banks of RONs simplifies the execution of subroutines and handling of interrupts, because. it is not necessary to transfer the contents of the RONs of the main program to the stack when calling the subroutine (it is enough to go to another active RON bank in the subroutine).

Access to the RPD is possible using indirect or direct byte addressing (direct byte addressing allows accessing only the first 128 bytes of the RPD).

The extended RPD area (for microcontrollers of the MCS-52 family and subsequent families) from address 128 (80h) to 255 (FFh) can only be addressed using the indirect addressing method.

Table 2 - Block Registers of Special Functions (s f r)

2. SOFTWARE MODEL MCS–51

COMMAND TYPES MCS–51

Almost half of the commands are executed in 1 machine cycle (MC). With a crystal oscillator frequency of 12 MHz, the execution time for such a command is 1 μs. The remaining commands are executed in 2 machine cycles, i.e. for 2 ms. Only multiplication (MUL) and division (DIV) instructions are executed in 4 machine cycles.

During one machine cycle, there are two accesses to the Program Memory (internal or external) to read two bytes of the instruction, or one access to the External Data Memory (EDM).

3. METHODS (METHODS) OF ADDRESSING MCS–51

1. REGISTER ADDRESSING - 8-bit operand is located in the RON of the selected (active) bank of registers;

2 DIRECT ADDRESSING (indicated by the sign - #) - the operand is located in the second (and for a 16-bit operand and in the third) byte of the command;

3 INDIRECT ADDRESSING (indicated by the - @ sign) - the operand is in the Data Memory (RPD or VPD), and the address of the memory cell is contained in one of the RONs of indirect addressing (R0 or R1); in the PUSH and POP commands, the address is contained in the stack pointer SP; the DPTR register can contain a VPD address up to 64K;

4 DIRECT BYTE ADDRESSING – (dir) – used to access RPD cells (addresses 00h…7Fh) and special function registers SFR (addresses 80h…0FFh);

5 DIRECT BIT ADDRESSING - (bit) - is used to address separately addressable 128 bits located in RPD cells at addresses 20H ... 2FH and to separately addressable bits of special function registers (see Table 3 and program model);

6 INDIRECT INDEX ADDRESSING (denoted by the @ sign) - simplifies viewing tables in the Program Memory, the PP address is determined by the sum of the base register (PC or DPTR) and the index register (Battery);

7 IMPLICIT (BUILT-IN) ADDRESSING - the instruction code contains an implicit (by default) reference to one of the operands (most often to the Accumulator).

4. PROCESSOR STATUS WORD (PSW) FORMAT

C - Carry (CARY) or borrow flag, also functions as a "boolean accumulator" in bit-operated instructions;

AC – auxiliary (additional) carry flag – set to "1" if the addition command (ADD, ADDC) had a carry from the low order tetrad to the high order (i.e. from the 3rd bit to the 4th bit);

F0 - user flag - set, reset and checked by software;

RS1,RS0 – Register bank selection:

OV - Arithmetic overflow flag; its value is determined by the XOR operation of the input and output carry signals of the most significant bit of the ALU; a single value of this flag indicates that the result of an arithmetic operation in the two's complement code is out of range: –128…+127; when performing the division operation, the OV flag is reset, and in the case of division by zero, it is set; when multiplying, the OV flag is set if the result is greater than 255 (0FFH);

Bit PSW - Reserved, contains a trigger, available for writing or reading;

P - parity flag - is the addition of the number of single bits in the accumulator to an even number; is formed by a combinational circuit (programmatically available only for reading).

The MCS-51 microcontrollers do not have the "Z" flag. But in the conditional jump instructions (JZ, JNZ), the combinational circuit checks the current (zero or non-zero) contents of the Accumulator.

All commands of transfers and exchange of operands can be carried out through the Accumulator (see Fig. 3). Moreover, transfers from / to External Memory (Program Memory or Data Memory) can only be carried out through the Battery.

Most transfers can also be made via a forward byte (dir). There are even dir-to-dir transfers (see Figure 3).

Missing transfers from RON to RON can be implemented as transfers from RON to the forward byte dir (given that the RONs are located in the initial area of ​​the Resident Data Memory, the cells of which can be addressed as dir).

XCH exchange commands allow you to send bytes without destroying both operands.

Arithmetic commands are executed only in the Accumulator. Therefore, the first operand must first be placed in the Accumulator and then add or subtract the second operand. The result is placed in the Accumulator.

The SUBB subtraction command is executed only with a borrow (i.e., the Cary flag is also subtracted from the result). Therefore, in order to execute a subtraction instruction without borrowing, it is necessary to first execute the Clear Flag C (CLRC) instruction.

The instruction for multiplying one-byte operands - MULAB - places a two-byte (16 bit) result: the low byte is in the Accumulator, the high byte is in register B.

The result of executing the instruction for dividing one-byte operands - DIVAB - is placed: the quotient - a Accumulator, the remainder - in register B.

The INC arithmetic instruction adds one to the selected operand. The DEC arithmetic instruction subtracts one from the selected operand. The Accumulator Decimal Correction (DAA) instruction helps you add binary coded decimal (BCD) numbers without converting them to hexadecimal (hex) format. The source operands must be in BCD format, i.e. in each tetrad of one byte there are only numbers from 0 to 9 (there cannot be hexadecimal numbers: A, B, C, D, E, F). Therefore, one byte can contain numbers from 00 to 99 for packed BCD numbers, or numbers from 0 to 9 for unpacked BCD numbers.

The DA A - decimal correction command performs actions on the contents of the Accumulator after adding BCD numbers in the processor (the numbers were added according to the laws of hexadecimal arithmetic) as follows (see example):

· if the content of the low-order tetrad of the Accumulator is greater than 9 or the auxiliary carry flag is set (AC = 1), then 6 is added to the content of the Accumulator (that is, the missing six digits in hex format);

· if after that the content of the high order of the Accumulator is greater than 9 or the flag C is set, then the number 6 is added to the high order of the Accumulator.

The decimal correction instruction DA A is not used after the increment instruction (INC) because the increment instruction does not affect (change) the C and AC flags.

Logic commands:

Logical "AND" - ANL,

Logical "OR" - ORL,

The XOR logical command - XRL - is executed in the Accumulator (as well as arithmetic), but it is possible to execute logical commands also in the direct address byte (dir). In this case, the second operand can be:

in the battery or

An immediate operand in an instruction.

Rotation instructions (RR A, RL A) and rotation instructions through the CARY flag (RRC A, RLC A) rotate the contents of the Accumulator by 1 bit. Bit operands are sent only through the C flag.

The architecture of the MCS-51 family is largely predetermined by its purpose - building compact And cheap digital devices. All functions of the microcomputer are implemented using a single microcircuit. The MCS-51 family includes a whole range of microcircuits from the simplest microcontrollers to quite complex ones. Microcontrollers of the MCS-51 family allow you to perform both the tasks of controlling various devices and implementing individual nodes of the analog circuit. All microcircuits of this family work with the same command system, most of them are performed in the same cases with matching pinout(numbering of legs for the case). This allows you to use chips from different manufacturers (such as Intel, Dallas, Atmel, Philips, etc.) for the developed device. without altering the circuit diagram of the device and program.

Figure 1. Structural diagram of the K1830BE751 controller

The block diagram of the controller is shown in Figure 1 and consists of the following main functional units: a control unit, an arithmetic logic unit, a timer/counter unit, a serial interface and interrupt unit, a program counter, data memory, and program memory. Bilateral exchange is carried out using an internal 8-bit data highway. Let's take a closer look at the purpose of each block. Almost all representatives of the MCS-51 family are built according to this scheme.. Various microcircuits of this family differ only in special-purpose registers (including the number of ports). Command system all controllers MCS-51 family contains 111 basic commands with a format of 1, 2 or 3 bytes and does not change when moving from one chip to another. This provides excellent portability of programs from one chip to another.

Control and synchronization unit

The control and synchronization unit (Timing and Control) is designed to generate synchronizing and control signals that ensure the coordination of the joint operation of the OEVM units in all permissible modes of its operation. The control unit includes:

• device for forming time intervals,
• I/O logic,
• instruction register,
• control register electricity consumption,
• command decoder, computer control logic.

Time slotting device is intended for generation and output of internal synchronization signals of phases, cycles and cycles. The number of machine cycles determines the duration of instruction execution. Almost all OEVM commands are executed in one or two machine cycles, except for the multiplication and division instructions, the duration of which is four machine cycles. Let us denote the frequency of the master oscillator through F g. Then the duration of the machine cycle is 12/F g, or 12 periods of the signal of the master oscillator. The input-output logic is designed to receive and issue signals that provide information exchange with external devices through input/output ports P0-P3.

Command register is designed to record and store an 8-bit operation code of the command being executed. The operation code, with the help of commands and computer control logic, is converted into a microprogram for executing the command.

Demand Control Register (PCON) allows you to stop the operation of the microcontroller to reduce power consumption and reduce the level of interference from the microcontroller. An even greater reduction in power consumption and noise reduction can be achieved by stopping the master oscillator of the microcontroller. This can be achieved by toggling bits in the PCON demand control register. For the n-MOS manufacturing option (1816 series or foreign chips that do not have a "c" in the middle of the name), the PCON power control register contains only one bit that controls the baud rate of the SMOD serial port, and there are no power consumption control bits.

Together with the article "Architecture of microcontrollers MCS-51" they read:

http://website/MCS51/tablems.php

http://website/MCS51/SysInstr.php

http://website/MCS51/port.php

UDC 681.5, 681.325.5 (075.8)

BBK 32.973.202-018.2 i 73

Shcherbina A. N.Computing machines, systems and networks. Microcontrollers and microprocessors in control systems: Cheb. allowance / A.N. Shcherbina, P.A. Nechaev-SPb.: From the Polytechnic. un-ta, 2012.-226 p.

Corresponds to the content of the state educational standard for areas of training and specialties in the field of management in technical systems, electric power industry and electrical engineering and the content of the exemplary curriculum of the discipline "Computers, systems and networks".

The fundamental questions of the logical organization of microprocessor systems are considered on the example of the basic architecture of the MCS-51 microcontroller family from Intel. The technology of programming microcontrollers in Assembler and SI languages ​​is described.

It can be useful for students and teachers of higher technical institutions, specialists in the automation of technological processes and production equipment, as well as for design engineers of microprocessor systems.

It also corresponds to the content of the state educational standard of the disciplines "Microcontrollers and microprocessors in control systems" and "Electronic devices of automation" for bachelor's, engineering and master's training in the direction 140400 "Electric power and electrical engineering".

Published by decision of the editorial and publishing council

St. Petersburg State Polytechnic University.

© Shcherbina A. N., Nechaev P. A., 2012

© St. Petersburg State

polytechnic university, 2012

ISBN 978-5-7422-3553-8

Introduction.. 7

Chapter 1. Architecture of the MCS51 family. 10

1.1 General characteristics 10

1.2 Block diagram 11

1.3 8051 microcontroller pin assignment 15

1.4 Memory organization 17

1.4.1 Program memory (ROM) 18

1.4.2 Data memory (RAM) 19

1.4.3 Registers of special functions. twenty

1.4.4 Flag Register (PSW) 23

1.5 Control and synchronization device 26

1.6 Organizing I/O ports 27

1.6.1 General information. 27

1.6.2 Alternative functions. 27

1.7. Timers / counters of microcontrollers of the 8051 family. 28

1.7.1. Structure of timers-counters. 28

1.7.2 Operating modes of timers-counters. thirty

1.8. Serial port 32

1.8.1. The structure of the serial port. 32

1.8.2. Transceiver control/status register SCON.. 34

1.8.3. Power control register PCON.. 36

1.9. Interrupt system 37

1.9.1. The structure of the interrupt system. 37

1.9.2 Execution of the interrupt routine. 40

Chapter 2 Features of 80C51GB.. microcontroller 42

2.1 Features 42

2.2 I/O ports P0-P5 43

2.2.1 Operation of I/O ports. 43

2.2.2 Writing to port.. 46

2.3 Features of the 8XC51GB.. interrupt system 49

Enable/disable interrupts. fifty

Interrupt priority management. 51

external interrupts. 54

2.3. ADC node 56

2.4. Hardware watchdog 61

2.5. Clock Failure Detection 63

2.6. Matrix of programmable counters RSA 64

2.6.1. Structure PCA.. 64

2.6.2. PCA Counter Mode Register (CMOD) 66

2.6.3. PCA counter control register (CON) 67

2.6.4. Compare/fix modules. 68

2.7. Enhanced Serial Port 76

2.8. Timers/Counters 79

Pin assignment of 8XC51GB.. group microcontrollers 86

Chapter 3 Programming MK 8051GB.. 89

3.1. Software model 89

3.2 Data types 93

3.3 Ways of addressing data 93

3.4 Command system 95

3.4.1 General characteristics. 95

3.4.2 Command types. 96

3.4.3 Types of operands. 97

3.4.4 Microcontroller data transfer commands. 98

3.4.5 Arithmetic instructions 8051.101

3.4.6 8051 MCU Logic Commands. 104

3.4.7 8051 Bit Operation Commands. 106

3.5 Debugging programs 111

Chapter 4. ASM-51 Programming Language. 112

4.2 Writing program text 113

4.3 Language alphabet. 114

4.4 Identifiers. 115

4.5 Numbers 117

4.6 Directives 118

4.7 Implementation of subroutines in ASM51 122

4.7.1 The structure of the subroutine-procedure in the ASM51 language. 122

4.7.2 Passing parameter variables to a subroutine. 123

4.7.3 Implementation of subprograms-functions in the ASM51 language. 123

4.7.4 Implementation of interrupt handling routines in the ASM51 language. 124

4.8 Structured programming in assembly language. 125

4.9 Peculiarities of translation of multi-module programs.. 126

4.10 Using segments 128

4.10.1 Partitioning the MK memory into segments .. 128

4.10.2 Absolute memory segments. 129

4.10.2 Relocatable memory segments. 131

Chapter 5. The C-51 Programming Language. 134

5.1 General characteristics of the language 134

5.3 Structure of C-51 programs 136

5.3. Elements of the C-51 programming language 138

5.3.1. Symbols.. 138

5.3.2. Lexical units, separators and the use of spaces. 141

5.3.3 Identifiers.. 142

5.3.4 Keywords. 143

5.3.5 Constants.. 143

5.4. Expressions in language statements 146

programming C-51 146

5.5. Operation Priorities 148

5.6. C-51 programming language statements 149

5.6.1. declaration operators. 150

5.6.2 Executable statements.. 150

5.6.3 Assignment operator. 151

5.6.4 Conditional statement. 151

5.6.5 Structural operator (). 152

5.6.6 Operator for loop. 152

5.6.7 Loop statement with condition check up to the while loop body. 153

5.6.8 Loop statement with condition check after loop body do while. 154

5.6.9 The break statement. 155

5.6.10 The continue statement. 155

5.6.11 Switch selection statement. 155

5.6.12 The goto operator. 157

5.6.13 Operator expression. 158

5.6.14 Return statement from subroutine return. 158

5.6.15 Empty statement. 158

5.7. Declaring Variables in the C-51 Programming Language. 159

5.7.1. Variable declaration. 159

5.7.3 Integer data types. 161

5.7.4 Floating point numbers. 162

5.7.5 Variables of enumerated type. 162

5.7.6. Declaring arrays in the C-51 programming language. 164

5.7.7. Structures.. 165

5.7.8. Associations (mixtures) 166

5.8. Using Pointers in C-51 167

5.8.1. Declaring pointers. 167

5.8.2. Untyped pointers. 168

5.8.3. Memory dependent pointers. 169

5.9. Declaring new types of variables 169

5.10. Data initialization 170

5.11. Using subroutines in the C-51 programming language. 170

5.11.1. Definition of subroutines.. 171

5.11.2. Subprogram parameters .. 173

5.11.3. Advance declaration of subroutines.. 174

5.11.4 Calling subroutines.. 176

5.11.5 Recursive subprogram call.. 176

5.11.6 Interrupt routines. 177

5.11.7 Scope of Variables and Subroutines.. 178

5.12. Multi-module programs 179

Chapter 6. Preparing Programs in the Keil μVision2 Integrated Development Environment. 182

6.1 Creating an ASM-51 project 182

6.2 Example of creating a C project for a training controller in the Keil μVision2 IDE 188

Chapter 7 Learning Controller Description .. 199

7.1. Controller structure 199

7.2. Address space 200

7.2.1. Memory allocation. 200

7.2.2 External memory. 201

7.2.3. Internal data memory. 202

7.3. I/O port allocation 202

7.4. Serial port………………………………...203

7.5. Working with LCD 205

7.6. Controller panels…………………………………………………213

APPENDIX P2 STRUCTURE OF THE REPORT ON LABORATORY WORK……..217

Appendix P3 Codes of machine commands. 217

References... 224

Introduction

In the development of specialties related to the automation of technological processes and industries, the study of microcontrollers is one of the important sections.

There is a continuous development and emergence of more and more 16- and 32-bit microcontrollers and microprocessors in the world, but the largest share of the world microprocessor market still remains with 8-bit devices. According to all forecasts of analytical companies for the near future, the leading position of 8-bit microcontrollers in the world market will continue.

Currently, among all 8-bit microcontrollers, the MCS-51 family is the undisputed leader in the number of varieties and the number of companies producing its modifications. It got its name from the first member of this family, the 8051 microcontroller. peripherals, flexible choice of external or internal program memory and reasonable price have made this microcontroller a success in the market.

Advantages of the MCS-51 family:

architecture, which is the de facto standard;

The extreme breadth of the family and the variety of opportunities;

Availability of high-performance and extended versions of processors;

a significant number of freely available software and hardware developments;

ease of hardware programming, including in-circuit programming;

low cost and availability of basic chips;

Availability of specialized versions of controllers for special conditions of use

Availability of versions of controllers with a reduced level of electromagnetic interference;

· wide popularity among the developers of the older generation, both in the world and in the CIS countries;

Support of architecture by leading educational institutions of the world.

And, finally, the main advantage: having mastered the basic chip of the family, it is easy to start working with such computing "monsters" as Cygnal, Dallas Semiconductor, Analog Devices, Texas Instruments microcontrollers.

The MCS-51 family includes a whole range of microcircuits from the simplest microcontrollers to quite complex ones. To date, there are more than 200 modifications of microcontrollers of the 8051 family, produced by almost 20 companies. Every year there are more and more variants of representatives of this family.

The main areas of development are:

increase in speed (increasing the clock frequency and redesigning the architecture);

reduction of supply voltage and power consumption;

increase in RAM and FLASH memory on a chip with the possibility of in-circuit programming;

· introduction of complex devices such as drive control systems, CAN and USB interfaces, etc. into the microcontroller periphery.

Microcontrollers of the MCS-51 family allow you to perform both the tasks of controlling various devices and implementing individual nodes of the analog circuit. All microcircuits of this family work with the same command system. Most of them are carried out in the same cases with the same pinout (numbering of the legs for the case). This makes it possible to use microcircuits of different manufacturers for the developed device without altering the circuit diagram of the device and the program.

The main manufacturers of varieties of the 51st family in the world are Philips, Siemens, Intel, Atmel, Dallas, Temic, Oki, AMD, MHS, Gold Star, Winbond, Silicon Systems and a number of others.

Characteristics of analogues of microcontrollers of the MCS-51 family (Intel 8XC51FA, 8XC51GB, 80C152) with advanced features are given in Table. IN 1.

Table B.1

Chapter 1 MCS51 Family Architecture

8-bit single-chip microcontrollers of the MCS-51 family have gained great popularity among developers of microprocessor control systems due to their well-designed architecture. The microcontroller architecture is a set of internal and external software-accessible hardware resources and a system of commands. The architecture of the MCS-51 family is largely determined by its purpose - the construction of compact and low-cost digital devices. Microcontrollers that perform all the functions of a microcomputer using a single microcircuit are called single-chip computers (OEVMs).

Intel has released about 50 models based on the operating core of the Intel 8051 microcontroller. At the same time, many other companies, such as Atmel, Philips, began production of their microcontrollers developed in the MCS-51 standard.

General characteristics

The main characteristics of the family:

8-bit CPU(CPU), focused on the control of executive devices;

· The CPU has a built-in circuit of 8-bit hardware multiplication and division of numbers;

The presence in the instruction set of a large number of operations for working with directly addressable bits makes it possible to talk about a processor for working with bit data (Boolean processor);

internal (on-chip) program memory of a mask or reprogrammable type, which has a volume of 4 to 32 Kb for various crystals, it is absent in some versions;

· at least 128 bytes of data resident RAM, which is used for organization, register banks, stack, and user data storage;

· at least 32 bidirectional interface lines (ports), individually configured for input or output of information;

· two 16-bit multi-mode counters/timers used to count external events, organize time delays and clock the communication port;

· bidirectional duplex asynchronous transceiver (UART), designed to organize communication channels between the microcontroller and external devices with a wide range of information transfer rates. There are means for hardware-software integration of microcontrollers into a connected system;

· a two-level priority interrupt system that supports at least 5 interrupt vectors from 4 internal and 2 external event sources;

built-in clock generator.

Structural scheme

The block diagram of the controller is shown in Figure 1.1 and consists of the following main functional units: a control unit, an arithmetic logic unit, a timer/counter unit, a serial interface and interrupt unit, a program counter, data memory, and program memory. Bilateral exchange is carried out using an internal 8-bit data highway. Almost all representatives of the MCS-51 family are built according to this scheme. Various microcircuits of this family differ only in special-purpose registers (including the number of ports).

Control and synchronization unit (Timing and Control)- designed to generate synchronizing and control signals that ensure the coordination of the joint operation of the OEVM units in all permissible modes of its operation. The control unit includes:

device for forming time intervals;

input-output logic;

instruction register;

electricity consumption management register;

command decoder, computer control logic.

Rice. 1.1. Structural diagram of the I8051 controller.

Time slotting device is intended for generation and output of internal synchronization signals of phases, cycles and cycles. The number of machine cycles determines the duration of instruction execution. Almost all OEVM commands are executed in one or two machine cycles, except for the multiplication and division instructions, the duration of which is four machine cycles. Let us denote the frequency of the master oscillator through F g. The duration of the machine cycle is 12/F g, or 12 periods of the signal of the master oscillator. The input-output logic is designed to receive and issue signals that ensure the exchange of information with external devices through the input/output ports P0-P3.

Command register is designed to record and store an 8-bit operation code of the command being executed. The operation code, with the help of a command decoder and computer control logic, is converted into a microprogram for command execution.

Demand Control Register (PCON) allows you to stop the operation of the microcontroller to reduce power consumption and reduce the level of interference from the microcontroller. An even greater reduction in power consumption and noise reduction can be achieved by stopping the master oscillator of the microcontroller. This can be achieved by toggling bits in the PCON demand control register. For the n-MOS manufacturing option (1816 series or foreign chips that do not have a "c" in the middle of the name), the PCON power control register contains only one bit that controls the baud rate of the SMOD serial port, and there are no power consumption control bits.

Arithmetic Logic Unit (ALU) is a parallel eight-bit device that provides arithmetic and logical operations. ALU consists of:

accumulator registers, holding registers TMP1 and TMP2;

ROM constants;

adder;

additional register (register B);

battery (ACC);

program status register (PSW).

Register accumulator and holding registers- eight-bit registers designed to receive and store operands for the duration of operations on them. These registers are not programmatically accessible.

ROM constants ensures the development of a correcting code for binary-decimal data representation, a mask code for bit operations, and a constant code.

Parallel 8-bit adder is a combination-type circuit with sequential transfer, designed to perform arithmetic operations of addition, subtraction and logical operations of addition, multiplication, inequivalence and identity.

Register B- an eight-bit register used during multiplication and division operations. For other instructions, it can be considered as an additional scratchpad register.

Battery- an eight-bit register designed to receive and store the result obtained when performing arithmetic-logical operations or shift operations

Serial Interface and Interrupt Block (SIP) designed to organize the input - output of sequential information flows and the organization of the program interrupt system. The block includes:

buffer PIP;

control logic;

control register;

transmitter buffer;

receiver buffer;

serial port transceiver;

interrupt priority register;

interrupt enable register;

interrupt flag processing logic and vector generation scheme.

Program Counter designed to form the current 16-bit address internal memory programs and 8/16-bit external program memory address. The program counter consists of a 16-bit PC buffer, a PC register, and an increment circuit (incrementing content by 1).

Data memory (RAM) is intended for temporary storage of information used during the execution of the program.

Ports P0, P1, P2, P3 are quasi-bidirectional input-output ports and are designed to ensure the exchange of information between the OEVM and external devices, forming 32 input-output lines.

Program Status Register (PSW) is designed to store information about the state of the ALU during the execution of the program.

Program memory (EPROM) designed to store programs and is a read-only memory (ROM). Various microcircuits use masked, UV-erasable or FLASH ROMs.

Data Pointer Register (DPTR) designed to store a 16 - bit address of external data memory.

Stack pointer (SP) is an eight-bit register designed to organize a special data memory area (stack), in which you can temporarily store any memory cell.

1.3 8051 microcontroller pin assignment(Fig. 1.2)

· U ss - the potential of the common wire ("earth");

U cc - main supply voltage +5 V;

· X1,X2 - conclusions for connection of a quartz resonator;

· RST - input of the general reset of the microcontroller;

PSEN - external program memory permission, issued only when accessing external ROM;

· ALE - external memory address strobe;

· EA - disable internal program memory; level 0 at this input causes the microcontroller to execute the program only from the external ROM; ignoring the inner (if the latter exists);

Rice. 1.2. Pin assignment 8051.

· P1 - eight-bit quasi-bidirectional input/output port, each bit of the port can be programmed both for input and output of information, regardless of the status of other bits;

· P2 - an eight-bit quasi-bidirectional port, similar to P1, the pins of this port are used to issue address information when accessing external program or data memory (if 16-bit addressing of the latter is used). In addition, port pins are used when programming to enter the high-order bits of the address into the microcontroller;

R3 - an eight-bit quasi-bidirectional port, similar to P1, the pins of this port can perform a number of alternative functions that are used in the operation of timers, a serial I / O port, an interrupt controller, and external program and data memory;

· P0 - multiplexed eight-bit bidirectional port of input-output of information, through this port at different points in time the low byte of the address and data are output.

Memory organization

The entire MCS-51 series has a Harvard architecture, i.e. separate program and data memory address spaces. The memory structure is shown in fig. 1.3.

The amount of internal (resident) program memory (ROM, EPROM or OTP ROM) located on a chip, depending on the type of microcircuit, can be 0 (ROMless), 4K (base chip), 8K, 16K or 32K. If necessary, the user can expand the program memory by installing an external ROM. Access to internal or external ROM is determined by the value of the signal at the EA (External Access) pin:

EA=V cc (supply voltage) - access to internal ROM;

EA=V ss (ground potential) - access to external ROM.

For ROMless chips, the EA pin must be permanently connected to V ss .

Rice. 1.3. Memory organization of the MCS-51 family

External ROM read strobe - (Program Store Enable) is generated when accessing external program memory and is inactive during access to the ROM located on the chip. The low program memory address area is used by the interrupt system. The 8051 base chip architecture supports five interrupt sources:

two external interrupts;

two interrupts from timers;

interrupts from the serial port.

On fig. 1.4 shows a map of the lower area of ​​program memory.

Rice. 1.4. Map of the lower area of ​​program memory

Program memory (ROM)

For microcontrollers of the 8051 family, program memory and data memory are independent and independent devices, addressed by various commands and control signals.

The amount of built-in program memory located on the 8051 microcontroller chip is 4 KB (in the family up to 32). When accessing external program memory, all 8051 microcontrollers always use a 16-bit address, which provides them with access to 64 KB of ROM. The microcontroller accesses program memory when reading the opcode and operands (using the PC program counter), as well as when executing instructions to copy a byte from program memory to the accumulator. When executing data copy commands, the addressing of the program memory cell from which data will be read can be carried out using both the PC counter and a special two-byte data pointer register DPTR.

Data memory (RAM)

The amount of on-chip data memory is 128 bytes. The external data memory can be up to 64 KB. The first 32 bytes are organized into four banks of general purpose registers, designated respectively bank 0 - bank 3. Each of them consists of eight registers R0-R7. At any time, the program is available, with register addressing, only one bank of registers, the number of which is contained in the third and fourth bits of the PSW program status word.

8051 Microcontroller Bit Area Addresses

Table 1.1

The remaining address space can be configured by the developer at his own discretion: it can accommodate the stack, system and user data areas. Data memory cells can be accessed in two ways. The first way is direct addressing of a memory cell. In this case, the cell address is the operand of the corresponding instruction. The second method is indirect addressing using pointer registers R0 or R1: before executing the corresponding command, one of them must contain the address of the cell to which it is necessary to access.

To access external data memory, only indirect addressing is used using registers R0 and R1 or using the 16-bit pointer register DPTR.

Part of the data memory is a bit area, it has the ability to use special bit commands to address each digit of the memory cells. The address of directly addressable bits can also be written in the form (ByteAddress).(Bit). The correspondence between these two addressing methods can be determined from Table. 1.1.

Microcontrollers of the MSS-51 family are built according to the Harvard architecture, in which the program memory and data memory are separated, have their own address spaces and ways to access them.

Program memory

The maximum amount of memory is 64K bytes, of which 4K, 8K, 16K or 32K bytes of memory (Table 7.3.1) are located on the chip, the rest is outside the chip.
When the voltage at the output EA = VCC both internal and external memory are used, with EA \u003d V CC \u003d 0 - only external memory.
Table 7.3.1 shows program memory addresses for the indicated cases.
The lower program memory area is reserved for starting the operation of the microcontroller ( starting address 0000h after reset) and for interrupt processing (interrupt addresses are located at 8-byte intervals: 0003h, 000Bh, 0013h, etc.).

The program memory is read-only, and when accessed:

● to external memory programs, the ¯PSEN signal is generated and a 16-bit address is always generated.
The low byte of the address is passed through port P0 in the first half of the machine cycle and is latched at the edge of the ALE strobe in the register.
In the second half of the cycle, port P0 is used to enter into the MCU a byte of data from external memory.
The high byte of the address is transmitted through the P2 port during the entire memory access time (Fig. 7.1.11);

● to internal memory the read signal is not generated and exchange cycles are used on the internal microcontroller bus.

Data memory

internal memory data can be conditionally divided into three blocks (Table 7.3.2).

Internal memory is always addressed by a byte, which provides addressing to only 256 memory locations.
Therefore, as can be seen from Table 7.3.2, for addressing the upper 8-bit cells of the internal RAM and the SFR special function registers occupying the same address space, the commands use different addressing methods: indirect and straight.

Features of the organization of the lower region of the internal RAM are reflected in Table 7.3.3.

Lower 32 bytes of internal RAM with addresses 00h.
1Fh are grouped into four banks of eight registers (R0.R7).
The next 16 bytes of RAM address 20h.
2Fh is an 8x16=128 bit memory area that allows each individual bit to be accessed.
To select the address of the bank register, its name R0 is used.
R7, for bank selection - bits RS0, RS1 of the PSW status word register.

Bit addresses

Bit addresses are given in Table 7.3.3.

Addressing is carried out direct way.

A list of all SFR special function registers with their addresses is given in Table 7.2.2.
For clarity, in Table 7.3.

4 is given register address mapSFR considered microcircuits of the MCS-51 family.
The SFR address is determined by the combination of column and row digits in hexadecimal.

For example, the CMOD register has address D9h.

For SFRs whose addresses end in 0h or 8h (shown in bold), in addition to byte allowed bitwise addressing.

In this case, the address of the bit occupying in register N-th bit, defined as XXh + ​​0Nh, where XXh is the address of the SFR register, N = 0.7.
Bit addresses in this area have values ​​from 80H to FFH.
For example, the bit addresses of the accumulator ACC lie within E0h-E7h.

External memory data (up to 64 KB) is created by additional memory chips connected to the MK.
To work with external data memory, special commands are used, so the address spaces of external and internal memory do not overlap and, therefore, both types of data memory can be used simultaneously.

To access the cells of the external data memory, use (Fig. 7.1.8):
● commands with indirect addressing;
● read signals ¯RD and write ¯WR;
● port P0 for transmitting the low byte of the address and receiving/transmitting data bytes;
● P2 port for transferring the high byte of the address.
Addressing methods.
The command system uses:
● direct, indirect, register, indirect-register, direct and index addressing (indirect addressing by sum of base and index registers) source operands;
● direct, register and indirect-register addressing destination operands.
The combination of these methods (addressing) provides 21 addressing modes.
In this and in the following tables of the command system, the following designations are used:

direct addressing.

With this addressing method, the location of a byte or bit of data is determined by the 8-bit address of the second (and third) byte of the instruction.
Direct addressing is only used to access internal data memory (lower 128 bytes of RAM) and special function registers.

register addressing.

This addressing method provides access to data stored in one of the eight registers R0.
R7 of the current bank of working registers.
It can also be used to access registers A, B, AB (dual register), pointer register DPTR, and carry flag C.
The address of these registers is embedded in the operation code, thereby reducing the number of command bytes.

Indirect register addressing.

In this case, the data address is stored in a pointer register whose location is determined by the opcode.
This addressing method is used to access the external RAM and the upper half of the internal RAM.
The registers-pointers of 8-bit addresses can be the registers R0, R1 of the selected bank of working registers or the stack pointer SP, for 16-bit addressing only the data pointer register DPTR is used.

direct addressing.

With this addressing method, the data is directly indicated in the command and is located in the second (or in the second and third) bytes of the command, i.e.
no memory addressing required.
For example, the command MOV A,#50 loads the number 50 into accumulator A.

index addressing.

This method is register-indirect addressing, in which the data byte address is determined as the sum of the contents of the base (DPTR or PC) and index (A) registers.
Way used only to access program memory and only in read mode; it simplifies the viewing of tables stored in program memory.

Command structure.

The command length is one (49 commands), two (45 commands) or three (17 commands) bytes.
The first byte of the command always contains the op-code (KO), while the second and third bytes are the addresses of operands or immediate data values.

Individual bits, tetrads, bytes and double-byte words can be used as operands.
There are 13 types of commands, which are given in Table 7.3.5:

● A, PC, SP, DPTR, Rn (n = 0, 7) - accumulator, program counter, stack pointer, data pointer register and current bank register;
● Rm (m = 0, 1) — current bank register used for indirect addressing;
● direct — 8-bit address of the directly addressed operand;
● bit — address of a directly addressable bit;
● rel — relative transition address;
● addr11, addr16 — 11- and 16-bit absolute jump address;
● #data8, #data16 — direct data (operands) of 8- and 16-bit lengths;
● A10, A9, A0 - separate digits of the 11-bit address;
● (.) — contents of the memory cell at the address specified in brackets;
● SB, MB - high and low bytes of the 16-bit operand.

General information about the command system.

The command system provides great data processing capabilities in the form of bits, tetrads, bytes, double-byte words, as well as real-time control.
The macro assembler language ASM51 is used to describe commands. The syntax of most commands consists of a mnemonic (abbreviation) for the operation to be performed, followed by operands.
Operands are used to specify various ways addressing and data types.

In particular, the abbreviation MOV has 18 different commands designed to process three types of data (bits, bytes, addresses) in different address spaces.
The set of commands has 42 mnemonic designations of 111 types of commands for specifying 33 MC functions.

Of the 111 instructions, 64 are executed in one machine cycle, 45 in two cycles, and only two instructions (MUL - multiplication and DIV - division) are executed in 4 cycles. With a clock frequency of 12 MHz, the duration of the machine cycle (12 cycles) is 1 µs. By functional feature commands can be divided into five groups. Below is a description of the commands of each group, presented in the form of tables. For the compactness of the tables, we select a group of commands (Table 7.3.6), the execution of which affects(marked with +) on the state of the flags register status word PSW.

Data transfer commands

Send commands can be divided into separate subgroups.
Commands for sending and exchanging data between internal memory cells(Table 7.3.7).

Commands 1-16, having the mnemonic MOV dest, src, are for forwarding byte or two bytes (command 16) of data from the source src to the destination dest, while:
● to indicate source(src) four addressing methods are used: register (commands 2-4, 6, 8), direct (commands 1, 7, 9, 11), indirect (commands 5, 10) and direct (commands 12-16);
● to indicate receiver(dest) three methods are used: register (commands 1, 3…5, 9, 12, 14, 16), direct (commands 2, 7, 8, 10, 13), indirect (commands 6, 11, 15).

Teams 17-20 provide exchange information between two cells of the internal data memory (or two-way transfer).
When executing XCH commands, bytes are exchanged, while XCHD commands are exchanged with lower tetrads of byte operands.

One of the cells is always the accumulator A. One of the registers Rn of the current bank is used as the other cell in the byte exchange, A is also a directly or indirectly addressed internal memory cell; when exchanging tetrads - only an indirectly addressed internal memory cell.

Since in all MKs the stack is located in the internal RAM, the same subgroup includes commands(20, 21) stack accesses PUSH src, POP dest.
These commands use only the direct addressing method, writing a byte to the stack or restoring it from the stack.
It should be borne in mind that in those MKs that do not have the upper 128 bytes in RAM, increasing the stack beyond 128 bytes leads to data loss.

Commands for transferring data between internal and external data memory(Table 7.3.8).

These commands use only indirect addressing, while a one-byte address can be located in P0 or R1 of the current register bank, A two-byte address can be in the DRTR data pointer register.
With any access to external memory, the role of the receiver or source of operands in the internal memory is played by the accumulator A.

Commands for transferring data from program memory(Table 7.3.9).

These instructions are for reading tables from program memory.

The MOVC A,@A + DPTR instruction is used to access a table with 0 to 255 inputs.

The number of the desired table entry is loaded into the accumulator, and the DPTR register is set to the start point of the table. A distinctive feature of another command is that the program counter PC is used as the base pointer and the table is accessed from the subroutine. First, the number of the required entry point is loaded into the accumulator, then the subroutine is called with the instruction MOVC A, @ A + PC. The table can have 255 entries, numbered 1 to 255, since 0 is used for the address of the RET command to exit the subroutine.

Commands for arithmetic data processing. All arithmetic commands are performed on unsigned integers. Operations on two operands(Table 7.3.10). In operations addition ADD, addition with carry ADDC and loan deductions SUBB:

● the source of one 8-bit operand and the receiver of the result is the accumulator;
● the source of another operand is either one of the working registers Rn (n = 0-7) of the current bank, or directly direct or indirectly @Rm (m = 0, 1) addressable RAM memory location, or direct data #data.

Operations multiplication MUL and division DIVs are executed on the contents of registers A and B. When multiplying, the upper 8 bits of the result are written to register B, the lower 8 bits to register A.
If the product is greater than 255, the overflow flag OV is set; the carry flag C is always reset. The DIV instruction divides the 8-bit accumulator A operand by the 8-bit register B operand.
When dividing, the quotient (most significant bits) is written to the register in A, the remainder (lower bits) - in B. The carry flags C and overflow OV are reset.
An attempt to divide by 0 sets the overflow flag OV. The division operation is more commonly used for shifts and base conversions.

When dividing binary number by 2 N it is shifted N bits to the left.
Extra bits are transferred to register B.

Operations on single-byte operands(Table 7.3.11).

The DA instruction is used to perform BCD operations. Instructions INC, DEC allow you to respectively increase or decrease the contents of the memory cell by one.
They apply to the contents of the accumulator A, one of the working registers Rn, or a memory cell addressed both directly and indirectly.
The increment operation also applies to the contents of the 16-bit DPTR pointer register.

Commands of logical operations.

Double operations

(Table 7.3.12).

The AML, ORL, XRL commands allow you to perform three binary logical operations on 8-bit operands: ANL - logical multiplication (AND), ORL - logical addition (OR), XRL - exclusive OR (XOR).
Operations are performed on individual bits of the operands. The source of one of the operands and at the same time the receiver of the result is either an accumulator (A) or a directly addressable memory cell (direct).
For the source of another operand, register, direct, indirect, or direct addressing is used.

Single operations

(Table 7.3.13).
The group also includes a number of single operations on the contents of the accumulator A: operations of clearing (CLR), logical addition or inversion (CPL), cyclic and extended cyclic shifts by 1 bit to the right (RL, RLC) and left (RR, RRC), exchange tetrad or cyclic byte shift by 4 bits (SWAP), A also an empty operation (NOP), as a result of which the state of all MK registers (with the exception of the program counter) remains unchanged.

Control Transfer Commands

Unconditional Jump Commands

(Table 7.3.14).

Commands 1-3 differ only in the format of the destination address.

The LJMP (L - Long) command performs a "long" unconditional jump to the specified address addr16, loading the PC counter with the second and third bytes of the command.
The command provides a transition to any point in the 64K byte address space.

The AJMP (A - Absolute) command provides an "absolute" jump to an address within a 2K byte page, the starting address of which is set by the most significant five bits of the PC program counter (initially, the contents of the PC increase by 2).

The SJMP (S - Short) command allows you to perform a "short" unconditional jump to the address, which is calculated by adding the signed offset rel in the second byte of the command with the contents of the PC counter, previously increased by 2.

The jump address is within -128+127 bytes relative to the command address.
To jump to any other point in the 64-kilobyte address space, command 4 with indirect @A+DPTR addressing can also be used.
In this case, the content of A is interpreted as an unsigned integer.

An empty operation (NOP), as a result of which the state of all microprocessor registers (with the exception of the program counter) remains unchanged.

Conditional Jump Instructions

(Table 7.3.15).

The instructions JZ and JNZ jump if the contents of the accumulator are respectively equal or non-zero.
The jump address is calculated by adding the relative sign offset rel to the content of the PC instruction counter after adding the number 2 (the length of the instruction in bytes) to it.

The content of the accumulator remains unchanged.
Commands do not affect flags.

CJNE commands (3-6) are used to implement a conditional jump based on the result of comparing two 8-bit operands, the location of which is specified in the commands.
If their values ​​are not equal, a transition is made.

The jump address is calculated by adding the offset rel to the contents of the PC counter, previously increased by 3.
IN otherwise the following command is executed.

The Algorithm column shows the influence of the values ​​of the compared 8-bit operands on the carry flag C.
DJNZ commands (7, designed to organize program cycles.

The register Rn or directly (direct) addressable cell is a counter of repetitions of the cycle, A offset rel (in the second and third bytes of commands) is the relative address of the transition to the beginning of the cycle.
When commands are executed, the contents of the counter are decremented by one and checked for zero.
If the content of the counter is not equal to zero, the transition to the beginning of the loop is performed.
Otherwise, the following command is executed.

The jump address is calculated by adding the offset to the contents of the counter, previously increased by the command length (by 2 or 3).
Command flags are not affected.

Commands for calling subroutines and returning from programs

(Table 7.3.16).
The LCALL "long call" and ACALL "absolute call" commands perform unconditional call subroutine located at the specified address.

The difference between these commands and the unconditional jump commands discussed above is that they save the return address (the contents of the counter) to the main program on the stack.
The return instruction from the RET subroutine restores the contents of the program counter from the stack, and the RETI instruction also enables service level interrupts.

Control transfer commands make extensive use of relative addressing, which supports relocatable program modules.
The relative address is an 8-bit signed offset rel, which provides branching from the current position of the PC counter in both directions by ±127 bytes.

Either the direct address addr16 or the indirect @A+DPTR address can be used to jump to any other point in the 64K-byte address space.
In the latter case, the content of A is interpreted as an unsigned integer.

Variant of short direct addressing addr11 inside 2K-byte current page introduced for compatibility with the MK48 architecture.

All of these addressing types can only be applied to a jump operation, while only direct addr16 and internal addr11 addressing methods are allowed for a call operation.
All conditional operations can only use relative addressing.

When the MK51 recognizes an interrupt request, it generates one of the LCALL addr16 instructions, which automatically stores the return address on the stack.
However, unlike the MK48, the MK51 does not have automatically stored status information.

In this case, the interrupt logic stops responding to requests of the level that was accepted for service.
To lower the interrupt level, the RETI interrupt return command is used, which, in addition to the operation equivalent to RET, includes the interrupt enable operation given level.
Typical conditional operations MK51 also include operations JZ, JNZ.
However, there is a new operation "Compare and go" CJNE.

According to this command, the operand is first compared according to the rules for subtracting integers with a constant and, in accordance with the result of the comparison, the CY flag is set. Then, in case of a mismatch with the constant, branching is performed. By comparing an accumulator, register, or memory location with a sequence of constants, we get a convenient way to check for matches, for example, to identify special cases.

In fact, the CJNE command is an element of a high-level language operator of the CASE type.

The DJNZ team has been further developed.
Now the programmer can use not only one of the working registers Rn as a counter, but also any DSEG memory cell.

Bit operation commands.

The group consists of 12 commands that allow you to perform operations on one or two bits (reset, set, bit inversion, A also logical AND and OR), and 5 commands designed to implement conditional transitions (Table 7.3.17).

The commands provide direct addressing of 128 bits located in sixteen cells of the internal RAM with addresses 20h.
2Fh (Table 7.3.3), and 128 bits located in special-purpose registers whose addresses are multiples of eight (highlighted in bold in Table 7.3.4).

When performing operations on two single-bit operands, the trigger of the PSW register is used as a logical accumulator, which stores the carry flag C (Table 7.1.2).

MOV (1,2) commands perform forwarding bit from one directly addressable bit cell of internal RAM to flip-flop C or vice versa.
Commands CRL (3, 4), SETB (5, 6) respectively dumped to zero or install to one carry flag C or the specified bit.
Using the CPL, ANL, ORL (7-12) commands, the logical operations of inversion, addition and multiplication are performed.

The group also includes commands (13-17) for implementing conditional jump operations with a relative 8-bit offset rel.
Transitions can be implemented both when the bit or the carry flag is set (commands 13, 16), and when it is cleared (commands 14, 17).

The JBC command, in addition to jumping to the computed address, when the condition (bit) = 1 is met, resets this bit to zero.
When executing conditional jump instructions, the jump address is calculated after adding the numbers 3 or 2 (reflecting the number of bytes in the instruction) to the contents of the counter.

LECTURE PLAN

1. Introduction

2. Arithmetic and logical instructions

3. Data transfer commands

4. Boolean operations

5. Jump instructions

1. Introduction

Command system MCS-51 supports a single set of instructions that is designed to execute 8-bit algorithms for controlling actuators. It is possible to use fast methods of addressing the internal RAM, performing bit operations on small data structures. There is an extensive system for addressing single-bit variables as an independent data type, which allows using individual bits in logical and control commands of Boolean algebra.

Addressing modes : instruction set MCS-51 supports the following addressing modes. Direct Addressing: The operand is specified by an 8-bit address in the instruction. Direct addressing is only used for the lower half of the internal data memory and registers SFR. indirect addressing: The instruction addresses the register containing the address of the operand. This type of addressing is used for external and internal RAM. Registers can be used to specify 8-bit addresses R0 And R1 selected register bank or stack pointer SP. For 16-bit addressing, only the data pointer register is used. DPTR.

Register instructions : registers R0–R7 the current register bank can be addressed via specific instructions containing a 3-bit field indicating the register number in the instruction itself. In this case, there is no corresponding address field in the command. Operations using special registers: some instructions use individual registers (for example, accumulator operations, DPTR, etc.). In this case, the address of the operand is not specified at all in the instruction. It is predetermined by the opcode.

Immediate Constants : the constant can be directly in the command behind the opcode.

Index Addressing : Indexed addressing can only be used to access program memory and only in read mode. In this mode, the tables in the program memory are viewed. 16-bit register ( DPTR or program counter) indicates the base address of the desired table, and the accumulator indicates the entry point to it.

Command sethas 42 command mnemonics to specify 33 functions of this system. The syntax of most assembly language instructions consists of a function mnemonic followed by operands specifying addressing methods and data types. different types data or addressing modes are determined by the set operands, not by changes in mnemonic notation.

The command system can be conditionally divided into five groups: arithmetic commands; logical commands; data transfer commands; bit processor instructions; branch and transfer commands. The designations and symbols used in the command system are given below.

Table. Notations and symbols used in the command system

Function mnemonics are uniquely associated with specific combinations of addressing methods and data types. In total, 111 such combinations are possible in the command system.

2. Arithmetic and logical instructions

How to example arithmetic instruction, the addition operation can be performed by one of the following commands.

ADDA,7 F 16 - add the number 7 to the contents of register A F 16 and save the result in register A;

ADDA,@ R0 - add to the contents of register A the number whose address (@ – commercial at ) is stored in the register R 0 (indirect addressing), and store the result in register A;

ADD A,R7- add to the contents of register A the contents of the register R 7 and save the result in register A;

ADD A,#127- add to the contents of register A a number whose storage cell address is 127 ( # - number symbol), and save the result in register T- re A.

All arithmetic instructions are executed in one machine cycle except for the instruction INC DPTR(data pointer offset DPTR to the next byte), requiring two machine cycles, as well as multiplication and division operations performed in 4 machine cycles. Any byte in the internal data memory can be incremented and decremented without using the accumulator.

Instruction MUL AB performs a multiplication (multiplication) of the data in the accumulator with the data in register B, placing the product in registers A (lower half) and B (higher half).

Instruction DIV AB divides (division) the content of the accumulator by the value in register B, leaving the remainder in B and the quotient in the accumulator.

Instruction DA A designed for binary-decimal arithmetic operations (arithmetic operations on numbers represented in binary-decimal code). It does not convert binary to binary decimal, but only provides the correct result when adding two BCD numbers.

Example logical command: logical AND operation can be performed by one of the following commands:

ANLA,7 F 16 - logical multiplication of the contents of register A by the number 7 F 16 and the result is stored in register A;

ANLA,@ R1 - logical multiplication of the contents of register A by the number whose address is stored in the register R 1 (indirect addressing), and store the result in register A;

ANL A,R6- logical multiplication of the contents of register A by the contents of the register R 6, and store the result in register A;

ANL A,#53 - logical multiplication of the contents of register A by a number whose storage cell address is 53 16, and save the result in register A.

All logical operations on the contents of the accumulator are performed in one machine cycle, the rest - in two. Boolean operations can be performed on any of the lower 128 bytes of internal data memory or on any register SFR (special function registers) in direct addressing mode without using the battery.

Rotate operations RL A, RLC A, etc. move the contents of the accumulator one bit to the right or left. In the case of a left cyclic shift, the least significant bit is moved to the most significant position. In the case of a right cyclic shift, the opposite occurs.

Operation SWAP A carries out the exchange of the junior and senior tetrads in the accumulator.

3. Data transfer commands

Command MOV dest,src allows data to be transferred between internal RAM cells or special function register area SFR without using a battery. In this case, work with the upper half of the internal RAM can only be carried out in the indirect addressing mode, and access to the registers SFR– only in direct addressing mode.

In all microcircuits MCS-51 the stack is placed directly in data resident memory and grows upwards. Instruction PUSH first increments the value in the stack pointer register SP, and then pushes data bytes onto the stack. Teams PUSH And POP are only used in direct addressing mode (when writing or restoring a byte), but the stack is always available when indirectly addressing through a register SP. Thus, the stack can also use the top 128 bytes of data memory. The same considerations preclude the use of stack instructions for addressing registers. SFR.

Data transfer instructions include a 16-bit transfer operation MOV DPTR,#data16, which is used to initialize the data pointer register DPTR when viewing tables in program memory or for accessing external data memory.

Operation XCH A,byte used to exchange data between the accumulator and the addressed byte. Command XCHD A,@Ri similar to the previous one, but only for lower tetrads involved in the exchange of operands.

Only indirect addressing is used to access the external data memory. In the case of single-byte addresses, registers are used R0 or R1 the current register bank, and for 16-bit ones, the data pointer register DPTR. With any method of accessing external data memory, the battery plays the role of a source or receiver of information.

To access tables located in program memory, the following commands are used:

MOVC A,@A+ DPTR ;

MOVC A,@A+ PC .

The contents of the corresponding data pointer register are used as the base address of the table. DPTR or PC(software counter), and the offset is taken from A. These instructions are used exclusively to read data from program memory, not to write to it.

4. Boolean operations

Microcircuits MCS-51 contain a Boolean processor. Internal RAM has 128 directly addressable bits. Special function register space SFR can also support up to 128 bit fields. Bit instructions perform conditional jumps, transfers, resets, inversions, AND and OR operations. All specified bits are available in direct addressing mode.

Carry bit CF in the special function register "program status word PSW' is used as a one-bit Boolean processor accumulator.

5. Jump instructions

Jump operation addresses are denoted in assembly language by a label or a real value in the program memory space. Conditional branch addresses are assembled into a relative offset - a sign byte added to the program counter PC if the transition condition is met. The boundaries of such jumps lie between minus 128 and 127 relative to the first byte following the instruction. In the special function register "program status word PSW» there is no zero flag, so the instructions JZ And JNZ check the condition "equals to zero" as testing the data in the accumulator.

There are three types of unconditional branch instruction: SJMP, LJMP And AJMP– destination addresses that differ in format. Instruction SJMP encodes the address as a relative offset, and occupies two bytes. The jump distance is limited to a range of minus 128 to 127 bytes relative to the instruction following SJMP.

In the instructions LJMP the destination address is used as a 16-bit constant. The command is three bytes long. The destination address can be located anywhere in program memory.

Command AJMP uses an 11-bit address constant. The command consists of two bytes. When this instruction is executed, the lower 11 bits of the address counter are replaced with the 11-bit address from the instruction. The five most significant bits of the program counter PC remain unchanged. Thus, the jump can be made inside the 2K-byte block, which contains the instruction following the instruction AJMP.

There are two types of subprogram call instructions: LCALL And ACALL. Instruction LCALL uses the 16-bit address of the called subroutine. In this case, the subroutine can be located anywhere in the program memory. Instruction ACALL uses the 11-bit subroutine address. In this case, the called subroutine must be located in the same 2K-byte block with the instruction following ACALL. Both versions of the instruction push the address of the next instruction onto the stack and load it into the program counter. PC the corresponding new value.

The subroutine ends with the instruction RET, allowing you to return to the instruction following the command CALL. This instruction pops the return address off the stack and loads it into the program counter. PC . Instruction RETI used to return from interrupt routines. The only difference RETI from RET is that RETI Informs the system that interrupt processing has completed. If at the time of execution RETI there are no other interrupts, it is identical RET.

Instruction DJNZ designed for cycle control. To run a loop N once you need to load into the counter bytes with the value N and close the loop body with the command DJNZ, indicating the beginning of the cycle.

Command CJNE compares its two operands as unsigned integers and jumps to the address specified in it if the compared operands are not equal. If the first operand is less than the second, then the carry bit CF set to "1".

All instructions in assembled form occupy 1, 2 or 3 bytes.